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19-3855; Rev 1; 4/06
2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN
General Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E low-capacitance 30kV ESD-protection diode arrays are designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The MAX13202E/MAX13204E/MAX13206E/MAX13208E protect against ESD pulses up to 15kV Human Body Model (HBM) and 30kV Air-Gap Discharge, as specified in IEC 61000-4-2. These devices have a 6pF oncapacitance per channel, making them ideal for use on high-speed data I/O interfaces. The MAX13204E is a quad-ESD structure designed for Ethernet and FireWire(R) applications. The MAX13202E/ MAX13206E/MAX13208E are 2-channel, 6-channel, and 8-channel devices. They are designed for cellphone connectors and SVGA video connections. These devices are available in 6-, 8-, and 10-pin DFN packages and are specified over the -40C to +125C automotive operating temperature range.
Features
High-Speed Data-Line ESD Protection 15kV--Human Body Model 30kV--IEC 61000-4-2, Air-Gap Discharge Tiny DFN Package MAX13202E (1mm x 1.5mm) MAX13204E (2mm x 2mm) MAX13206E (2mm x 2mm) MAX13208E (2mm x 2mm) Low 6pF Input Capacitance Low 1nA (max) Leakage Current +0.9V to +16V Supply Voltage Range
MAX13202E/MAX13204E/MAX13206E/MAX13208E
Ordering Information
PART MAX13202EALT+ MAX13204EALT+ MAX13206EALA+ MAX13208EALB+ PINPKG 6 DFN 6 DFN 8 DFN 10 DFN PROTECTED I/O PORTS 2 4 6 8 TOP MARK BV AAO AAL AAD PKG CODE L611-1 L622-1 L822-1 L1022-1
Applications
USB USB 2.0 PDAs FireWire Ethernet Video Cell Phones
Pin Configurations
GND N.C. I/O2
Note: All devices are specified over the -40C to +125C automotive operating temperature range. +Denotes lead-free package
Typical Operating Circuit
VCC VCC
6
5
4
MAX13202E
+ 1 VCC 2 N.C. 3 I/O1 0.1F PROTECTED CIRCUIT I/0 I/0_
0.1F
DFN (1mm x 1.5mm) Pin Configurations continued at end of data sheet.
MAX13202E MAX13204E MAX13206E MAX13208E
FireWire is a registered trademark of Apple Computer, Inc. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN MAX13202E/MAX13204E/MAX13206E/MAX13208E
ABSOLUTE MAXIMUM RATINGS
VCC to GND ............................................................-0.3V to +18V I/O_ to GND ................................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 6-Pin, 1mm x 1.5mm DFN (derate 2.1mW/C above +70C)................................................................168mW 6-Pin, 2mm x 2mm DFN (derate 4.5mW/C above +70C)................................................................358mW 8-Pin, 2mm x 2mm DFN (derate 4.8mW/C above +70C)................................................................381mW 10-Pin, 2mm x 2mm DFN (derate 5.0mW/C above +70C)................................................................403mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Junction Temperature .....................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V 5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25C.) (Note 1)
PARAMETER Supply Voltage Supply Current Diode Forward Voltage SYMBOL VCC ICC VF IF = 10mA TA = +25C, 15kV, Human Body Model, IF = 10A Channel Clamp Voltage (Note 2) VC TA = +25C, 14kV, Contact Discharge (IEC 61000-4-2), IF = 42A TA = +25C, 30kV, Air-Gap Discharge (IEC 61000-4-2), IF = 90A Channel Leakage Current (Note 3) Channel Input Capacitance ESD PROTECTION Human Body Model IEC 61000-4-2 Contact Discharge IEC 61000-4-2 Air-Gap Discharge MAX13204E/MAX13206E/MAX13208E MAX13202E 15 14 12 30 kV kV kV TA = -40C to +50C TA = -40C to +125C VCC = 5V, bias of VCC/2, f = 1MHz (Note 3) Positive transients Negative transients Positive transients Negative transients Positive transients Negative transients -1 -1 6 0.65 CONDITIONS MIN 0.9 1 TYP MAX 16.0 100 0.95 VCC + 25 -25 VCC + 80 V -80 VCC + 120 -120 +1 +1 7 nA A pF UNITS V nA V
Note 1: Limits over temperature are guaranteed by design, not production tested. Note 2: Idealized clamp voltages (L1 = L2 = L3 = 0) (Figure 1); see the Applications Information section for more information. Note 3: Guaranteed by design. Not production tested.
2
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN MAX13202E/MAX13204E/MAX13206E/MAX13208E
Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX13204E//6E/8E toc01
CLAMP VOLTAGE vs. DC CURRENT
MAX13204E//6E/8E toc02
I/O LEAKAGE CURRENT vs. TEMPERATURE
MAX13204E//6E/8E toc03
100
1.1
10
10 SUPPLY CURRENT (nA)
I/O LEAKAGE CURRENT (nA)
CLAMP VOLTAGE (V)
1.0 I/O TO VCC 0.9
1 VCC = 12V VCC = 5V 0.1
1 VCC = 12V 0.1
0.8 0.01 VCC = 5V 0.001 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) VCC = 3.3V 0.7 30 50 70 90
I/O TO GND
0.01
VCC = 3.3V
0.001 110 130 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) DC CURRENT (mA)
INPUT CAPACITANCE vs. INPUT VOLTAGE
MAX13204E/6E/8E toc04
INPUT CAPACITANCE vs. INPUT VOLTAGE
9 INPUT CAPACITANCE (pF) 8 7 6 5 4 3 2 1 0 VCC = 12V
MAX13204E/6E/8E toc05
14 13 12 INPUT CAPCITANCE (pF) 11 10 9 8 7 6 5 4 0 1 2 3 4 5 INPUT VOLTAGE (V) VCC = 5.0V VCC = 3.3V
10
0
1
2
3
4
5
6
7
8
9 10 11 12
INPUT VOLTAGE (V)
Pin Description
PIN MAX13202E 1 2, 5 3, 4 6 MAX13204E 1 -- 2-5 6 MAX13206E 1 -- 2-7 8 MAX13208E 1 -- 2-9 10 NAME FUNCTION
VCC N.C. I/O_ GND
Power-Supply Input. Bypass VCC to GND with a 0.1F ceramic capacitor. Place the capacitor as close as possible to the device. No Connection. Not internally connected. ESD-Protected Channel Ground
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN MAX13202E/MAX13204E/MAX13206E/MAX13208E
Detailed Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E are diode arrays designed to protect sensitive electronics against damage resulting from ESD conditions or transient voltages. The low input capacitance makes these devices ideal for high-speed data lines. The MAX13202E/MAX13204E/MAX13206E/MAX13208E protect two, four, six, and eight channels, respectively. The MAX13202E/MAX13204E/MAX13206E/MAX13208E are designed to work in conjunction with a device's intrinsic ESD protection. The MAX13202E/MAX13204E/ MAX13206E/MAX13208E limit the excursion of the ESD event to below 25V peak voltage when subjected to the Human Body Model waveform. When subjected to the IEC 61000-4-2 waveform, the peak voltage is limited to 80V (Contact Discharge) and 120V (Air-Gap Discharge). The device that is being protected by the MAX13202E/MAX13204E/ MAX13206E/MAX13208E must be able to withstand these peak voltages plus any additional voltage generated by the parasitic board. d(IESD ) d(IESD ) VC = - VF(D2) + L1 x + L3 x dt dt where IESD is the ESD current pulse.
POSITIVE SUPPLY RAIL
L2
D1 L1 I/O_ PROTECTED LINE D2
L3 GROUND RAIL
Applications Information
Design Considerations
Maximum protection against ESD damage results from proper board layout (see the Layout Recommendations section and Figure 2). A good layout reduces the parasitic series inductance on the ground line, supply line, and protected signal lines. The MAX13202E/MAX13204E/MAX13206E/MAX13208E ESD diodes clamp the voltage on the protected lines during an ESD event and shunt the current to GND or VCC. In an ideal circuit, the clamping voltage, VC, is defined as the forward voltage drop, VF, of the protection diode plus any supply voltage present on the cathode. For positive ESD pulses: VC = VCC + VF For negative ESD pulses: VC = -VF In reality, the effect of the parasitic series inductance on the lines must also be considered (Figure 1). For positive ESD pulses:
d(IESD ) d(IESD ) VC = VCC + VF(D1) + L1 x + L2 x dt dt
Figure 2. Layout Considerations
Figure 1. Parasitic Series Inductance
VCC L1 PROTECTED LINE NEGATIVE ESD CURRENT PULSE PATH TO GROUND
L2
D1 VC I/O_ D2 L3 PROTECTED CIRCUIT
GND
For negative ESD pulses:
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN
During an ESD event, the current pulse rises from zero to peak value in nanoseconds (Figure 3). For example, in a 15kV IEC-61000-4-2 Air-Gap Discharge ESD event, the pulse current rises to approximately 45A in 1ns (di/dt = 45 x 109). An inductance of only 10nH adds an additional 450V to the clamp voltage. An inductance of 10nH represents approximately 0.5in of board trace. Regardless of the device's specified diode clamp voltage, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. A low-ESR 0.1F capacitor must be used between VCC and GND. This bypass capacitor absorbs the charge transferred by a +14kV (MAX13204E/MAX13206E/ MAX13208E) and 12kV (MAX13202E) IEC61000-4-2 Contact Discharge ESD event. Ideally, the supply rail (VCC) would absorb the charge caused by a positive ESD strike without changing its regulated value. In reality, all power supplies have an effective output impedance on their positive rails. If a power supply's effective output impedance is 1, then by using V = I x R, the clamping voltage of VC increases by the equation V C = I ESD x R OUT . An 8kV IEC 61000-4-2 ESD event generates a current spike of 24A, so the clamping voltage increases by VC = 24A x 1, or VC = 24V. Again, a poor layout without proper bypassing increases the clamping voltage. A ceramic chip capacitor mounted as close to the MAX13202E/ MAX13204E/MAX13206E/MAX13208E V CC pin is the best choice for this application. A bypass capacitor should also be placed as close to the protected device as possible.
30kV ESD Protection
ESD protection can be tested in various ways. The MAX13202E/MAX13204E/MAX13206E/MAX13208E are characterized for protection to the following limits: * 15kV using the Human Body Model * 14kV (MAX13204E/MAX13206E/MAX13208E) and 12kV (MAX13202E) using the Contact Discharge method specified in IEC 61000-4-2 * 30kV using the IEC 61000-4-2 Air-Gap Discharge method ESD Test Conditions ESD performance depends on a number of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results.
MAX13202E/MAX13204E/MAX13206E/MAX13208E
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 100pF
STORAGE CAPACITOR
Figure 4. Human Body ESD Test Model
I 100% 90% IPEAK
IP 100% 90% AMPERES 36.8%
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
10% tR = 0.7ns to 1ns 30ns 60ns t
10% 0 0 tRL TIME tDL CURRENT WAVEFORM
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
Figure 5. Human Body Model Current Waveform 5
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN MAX13202E/MAX13204E/MAX13206E/MAX13208E
Layout Recommendations
RC 50 to 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 150pF
STORAGE CAPACITOR
Proper circuit-board layout is critical to suppress ESDinduced line transients. The MAX13202E/MAX13204E/ MAX13206E/MAX13208E clamp to 120V; however, with improper layout, the voltage spike at the device is much higher. A lead inductance of 10nH with a 45A current spike at a dv/dt of 1ns results in an ADDITIONAL 450V spike on the protected line. It is essential that the layout of the PC board follows these guidelines: 1) Minimize trace length between the connector or input terminal, I/O_, and the protected signal line. 2) Use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance to the power rails for shunted ESD current. 3) Ensure short ESD transient return paths to GND and VCC. 4) Minimize conductive power and ground loops. 5) Do not place critical signals near the edge of the PC board. 6) Bypass VCC to GND with a low-ESR ceramic capacitor as close to VCC and ground terminals as possible. 7) Bypass the supply of the protected device to GND with a low-ESR ceramic capacitor as close to the supply pin as possible.
Figure 6. IEC 61000-4-2 ESD Test Model
Human Body Model Figure 4 shows the Human Body Model, and Figure 5 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5k resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. The MAX13202E/ MAX13204E/MAX13206E/MAX13208E help users design equipment that meets Level 4 of IEC 61000-4-2. The main difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2. Because series resistance is lower in the IEC 61000-4-2 ESD test model (Figure 6), the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 3 shows the current waveform for the 8kV IEC 61000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized.
Chip Information
PROCESS: BiCMOS
6
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN
Functional Diagrams
MAX13202E VCC MAX13204E VCC MAX13206E VCC
MAX13202E/MAX13204E/MAX13206E/MAX13208E
I/O1
I/O2
I/O1
I/O2
I/O3
I/O4
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
GND
GND
GND
MAX13208E VCC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
GND
Pin Configurations (continued)
GND GND GND I/O8 I/O7 I/O6 7 4 I/O3 I/O4 I/O3 I/O6 I/O5 I/O4 I/O5 6 5 I/O4
6
5
4
8
7
6
5
10
9
8
MAX13204E
+ 1 VCC 2 I/O1 3 I/O2 + 1 VCC
MAX13206E
+ 2 I/O1 3 I/O2 4 I/O3 1 VCC
MAX13208E
2 I/O1
3 I/O2
6 DFN (2mm x 2mm)
8 DFN (2mm x 2mm)
10 DFN (2mm x 2mm)
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN MAX13202E/MAX13204E/MAX13206E/MAX13208E
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6L UDFN.EPS
TABLE1 Translation Table for Calendar Year Code Calendar Year 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 Legend: Marked with bar Blank space - no bar required TABLE2 Translation Table for Payweek Binary Coding Payweek 06-11 12-17 18-23 24-29 30-35 36-41 42-47 48-51 52-05 Legend: Marked with bar Blank space - no bar required
TITLE:
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
APPROVAL DOCUMENT CONTROL NO. REV.
-DRAWING NOT TO SCALE-
21-0147
D
2
2
8
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2-/4-/6-/8-Channel, 30kV ESD Protectors in DFN
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, 10L UDFN.EPS
MAX13202E/MAX13204E/MAX13206E/MAX13208E
D
A
e
b
N
XXXX XXXX XXXX
SOLDER MASK COVERAGE
E
PIN 1 0.10x45
L
PIN 1 INDEX AREA SAMPLE MARKING 7 1 A A
L1
(N/2 -1) x e)
C L
C L
b A A2 A1
L e
EVEN TERMINAL
L e
ODD TERMINAL
PACKAGE OUTLINE, 6, 8, 10L uDFN, 2x2x0.80 mm
-DRAWING NOT TO SCALE-
21-0164
A
1
2
COMMON DIMENSIONS SYMBOL A A1 A2 D E L L1 MIN. 0.70 0.15 0.020 1.95 1.95 0.30 NOM. 0.75 0.20 0.025 2.00 2.00 0.40 0.10 REF. MAX. 0.80 0.25 0.035 2.05 2.05 0.50
PACKAGE VARIATIONS PKG. CODE L622-1 L822-1 L1022-1 N 6 8 10 e 0.65 BSC 0.50 BSC 0.40 BSC b 0.300.05 0.250.05 0.200.03 (N/2 -1) x e 1.30 REF. 1.50 REF. 1.60 REF.
PACKAGE OUTLINE, 6, 8, 10L uDFN, 2x2x0.80 mm
-DRAWING NOT TO SCALE-
21-0164
A
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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